The most difficult problems in application specific integrated circuit (ASIC) design often involve meeting system I/O timing demands. IC delays can vary by 200-400% over all voltage, temperature, and process conditions. Moreover, clock frequency requirements of electronic systems are continually increasing resulting in increasingly complex clock synchronization requirements. Balancing the timing specifications of the many VLSI parts is a real challenge when delays are so variable. If this delay can be controlled, systems can be designed which more fully exploit the innate performance capabilities of their semiconductor components.
It is important to minimize on-chip clock distribution delay and total system clock skew in a system which uses ASICs in order to provide for safe data transfer between the ASICs. ASIC Phase Locked Loops (PLLs) are used most commonly to eliminate on-chip clock distribution delay. PLLs can eliminate delay in clock buffering by adding an adjustable delay which delays the output signal exactly one clock period relative to the input clock.
By eliminating on chip clock delay, the ASIC's clock to output delay variance and total system clock skew are also dramatically reduced. FIG. 1 shows an example of this. ASIC #1 and ASIC #2 in FIG. 1 both have on-chip PLLs. The system master clock is fed to both ASICs. The clocks are buffered through a PLL which includes a high fan-out clock driver in its feedback loop. This locks the high fan-out internal clock to the phase of the clock coming on-chip. The elimination of the clock tree and I/O delay can nearly double clocking rate between devices which are communicating synchronously to a system master clock.
There are two primary types of PLLs: analog phase locked loops (APLLs); and digital phase locked loops (DPLLs). The basic difference between the two is fairly straightforward. Some analog PLLs use a set delay chain to adjust delay and each element in the delay chain has its delay varied by analog bias voltages supplied by a phase detector, Digital phase locked loops do not adjust delays of any gates, but vary delays by adjusting how many delay steps are included in a delay chain. APLLs thus have continuous delay adjustment whereas DPLLs adjust delays in discrete steps.
The primary advantage of the APLL is that the jitter is very low compared to the step jitter of a DPLL. Although both PLL types can be implemented with mask programmable cells, APLLs require large amounts of SPICE simulation and design time to implement. DPLLs, on the other hand, can be designed with digital simulation only and provide large benefits in system performance while maintaining fast time to market. DPLLs also require no off-chip components and exhibit good immunity to noise. DPLLs can also be used to generate carefully controlled delay lines. These delay lines are often useful in designing memory interfaces, generating new clocks or resolving other difficult system timing problems. DPLLs can also be used as dynamic on-chip performance monitors.
Phase jitter is the most notable performance characteristic of a DPLL. It has a direct impact on the minimum achievable phase error one can expect in a phase locked system. Hence, it is advantageous to make the phase jitter as small as possible. In DPLL applications, the phase jitter is equal to the step size of the digital delay line. Thus, by making the step size of the digital delay line smaller, the effective phase jitter can be reduced resulting in more accurate phase locking capability.
Texas Instruments' TGB1000/TEB 1000 and TGC1000/TEC1000 arrays both offer variable delay line macros in their macro libraries. In each of the macros, the step size is designed to be as small as possible with available library macros. This step size is equal to the delay through a buffer and a transmission gate. The buffer is constructed with two inverters in series. This gives the smallest delay step (step size) achievable with library macros. As system frequencies increase, however, the size of this delay step becomes large relative to the system clock period. Thus, the resulting phase jitter in a locked system becomes a larger source of phase error. Therefore, it is necessary to design a new method of producing smaller delay steps to reduce the impact of phase jitter on clock skew for higher frequency ASIC applications.